The present invention is directed to a multiprocessor system of the type including a number of individual processor modules interconnected by a bus structure that provides communication therebetween and, more particularly, to a bus controller operable to grant access to the bus for each processor module and to determine a number indicative of the processor modules operably coupled to the bus.
Today, there exist a variety of multiprocessor system architectures, each using one or another of a number of available techniques to establish data communication between the individual processors. Each have their respective advantages and disadvantages. One such multiprocessor architecture, for example, uses a central memory in "mailbox" fashion to transfer messages between processors. Another architecture incorporates a bus structure that connects the individual, autonomously operating processors for providing interprocessor communication. Communication on the bus is, at times, controlled by a bus controller which operates, in response to requests for bus access from any one of the particular controllers, to poll the processors, select (in response to the poll) a processor/receiver pair for communication, and control that communication. This communication technique has the advantage of establishing a communication colloguy in a short time, allowing high data transfers to take place between the processors of the system. An example of this type of system can be found in U.S. Pat. No. 4,228,496 to Katzman, et al.
One drawback, however, is the amount of circuitry necessary to implement the communication system. Thus, if the system can operate to conduct interprocessor communication at a lower rate, utilizing a simpler protocol, less parts are needed, resulting in a less expensive and more reliable system to construct.